In semiconductor fabrication industry, electronic devices may be produced by fabricating a number of layers on a substrate, some or all of the layers including various structures. There is a need to control alignment between various layers of samples, or within particular layers of such samples. The relative position of such structures both within particular layers and with respect to structures in other layers is relevant and critical to the performance of completed electronic devices. The relative position of structures within such a sample is generally called overlay.
The measurement of overlay error between successive patterned layers on a sample is one of the most critical process control techniques used in the manufacturing of integrated circuits and devices. Overlay accuracy generally pertains to the determination of how accurately a first patterned layer aligns with respect to a second pattered layer disposed above or below it and to the determination of how accurately a first pattern aligns with respect to a second pattern disposed on the same layer.
Various technology and processes for overlay measurements have been developed and employed with varying degrees of success. In general, overlay measurements are performed with test patterns that are etched into the layers. The images of these test patterns may be captured by an imaging tool and an analysis algorithm is used to calculate the relative displacement of the patterns from the captured images. One of the most commonly used overlay target pattern is the “Box-in-Box” target, which includes a pair of concentric squares (or boxes) that are built into scribe lines between adjacent dies on successive layers of the wafer. The overlay error is generally determined by comparing the position of one square relative to another square. Another example of an overlay target pattern is the “bar in bar” target, which includes a plurality of parallel bars on successive layers of the wafer.
Another example of an overlay target pattern is a grating-type target. The target usually includes a first periodic test structure and a second periodic test structure. The first periodic test structure is placed on a first layer of a device and the second periodic structure is placed on a second layer of the device adjacent the first periodic test structure when the second layer is placed on the first layer. Any offset that may occur between the first and second periodic test structures may be detected optically, micro-mechanically or with electron beams. Such grating style targets (sometimes referred to as “AIM” marks) can be denser and more robust, than “box” type marks resulting in the collection of more process information, as well as target structures that can withstand the rigors of CMP. The use of such marks is described, e.g., by Adel et al in commonly assigned U.S. Pat. Nos. 6,023,338, 6,921,916 and 6,985,618, all three of which are incorporated herein by reference for all purposes.
Additionally, some efforts have been made to utilize radiation scatterometry as a basis for overlay metrology. Certain existing approaches to determining overlay from scatterometry measurements concentrate on comparison of the measured spectra to calculated theoretical spectra based on model shape profiles, overlay, and film stack, and material optical properties or comparison to a reference signal from a calibration wafer. Alternatively, various implementations of sub-optical multi-cell targets have been employed.
Accuracy of the overlay measurement is still one of the major challenges faced by the overlay metrology in advanced integrated circuit manufacturing in the 2× and 1× nm process nodes. One of the main issues with accuracy is the bias between the overlay of the overlay target and the overlay of the real device. It is known in the industry to have overlay excursions which are only seen at end of line yield and not detected inline by the overlay metrology. It was found in several cases that such yield loss can occur due to change in the target to device bias, which is not detected by the traditional overlay target. Several methods have been implemented in the industry to check the real device overlay. For example, after device de-capping from the oxide protecting the previous layer, critical dimension scanning optical microscopy (CD-SEM) can measure the real device overlay directly. Another example is doing a cross section of the device and measuring the real overlay directly with a scanning electron microscope (SEM) or TEM (Transmission Electron Microscope). Electrical testing has also been employed to calculate device-like test structures overlay from resistance measurements. Each method however has its limitations. Accordingly, there are continuing efforts to develop improved overlay measurement techniques or methods that may increase accuracy of the measurement.